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STK22C48
16-Kbit (2 K x 8) AutoStoreTM nvSRAM
16-Kbit (2 K x 8) AutoStore nvSRAM
Features

Functional Description
The Cypress STK22C48 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. A hardware STORE is initiated with the HSB pin.
25 ns and 45 ns access times Hands off automatic STORE on power-down with external 68 F capacitor STORE to QuantumTrapTM nonvolatile elements is initiated by software, hardware, or AutoStoreTM on power-down RECALL to SRAM initiated by software or power-up Unlimited read, write, and RECALL cycles 1,000,000 STORE cycles to QuantumTrap 100 year data retention to QuantumTrap Single 5 V +10% operation Commercial and industrial temperatures 28-pin 300 mil and (330 mil) Small outline integrated circuit (SOIC) package Restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
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Quantum Trap 32 X 512 STORE
A5 A6 A7 A8 A9
ROW DECODER
STATIC RAM ARRAY 32 X 512
RECALL
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V CC V CAP
POWER CONTROL STORE/ RECALL CONTROL
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HSB
DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
N
COLUMN I/O
INPUT BUFFERS
DQ 1
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
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OE
CE WE
Cypress Semiconductor Corporation Document Number: 001-51000 Rev. *D
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198 Champion Court
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San Jose, CA 95134-1709
* 408-943-2600 Revised March 7, 2011
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STK22C48
Contents
Pin Configurations ........................................................... 3 Device Operation .............................................................. 4 SRAM Read ....................................................................... 4 SRAM Write ....................................................................... 4 AutoStore Operation ........................................................ 4 AutoStore Inhibit mode .................................................... 4 Hardware STORE (HSB) Operation ................................. 5 Hardware RECALL (Power Up) ........................................ 5 Data Protection ................................................................. 5 Noise Considerations....................................................... 5 Hardware Protect.............................................................. 5 Low Average Active Power.............................................. 5 Preventing Store............................................................... 6 Best Practices................................................................... 6 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 DC Electrical Characteristics .......................................... 7 Data Retention and Endurance ....................................... 7 Capacitance ...................................................................... 8 Thermal Resistance .......................................................... 8 AC Test Conditions .......................................................... 8 AC Switching Characteristics ......................................... 9 SRAM Read Cycle ...................................................... 9 Switching Waveforms ...................................................... 9 SRAM Write Cycle ..................................................... 10 AutoStore or Power Up RECALL .................................. 11 Switching Waveform ...................................................... 11 Hardware STORE Cycle ................................................. 12 Switching Waveform ...................................................... 12 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Document Conventions ................................................. 15 Acronyms ................................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17
Document Number: 001-51000 Rev. *D
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STK22C48
Pin Configurations
Figure 1. Pin Diagram - 28-pin SOIC
V CAP NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
V CC WE HSB A8 A9 NC OE A 10 CE
28-SOIC
Top View
(Not To Scale)
23 22 21 20 19 18 17 16 15
DQ6 DQ5
Table 1. Pin Definitions Pin Name A0-A10 DQ0-DQ7 WE CE OE VSS VCC HSB VCAP NC W E G Alt
IO Type Input Input Input Input
Input or output Bidirectional data IO lines. Used as input or output lines depending on operation. Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground
Power supply Power supply inputs to the device.
Input or output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull-up resistor keeps this pin high if not connected (connection optional). Power supply AutoStore capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. No connect No connect. This pin is not connected to the die.
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Address inputs. Used to select one of the 2,048 bytes of the nvSRAM.
Ground for the device. The device is connected to ground of the system.
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Device Operation
The STK22C48 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK22C48 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. Figure 2. AutoStore Mode
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0-7 are written into the memory if it has valid tSD, before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor between 68 F and 220 F (+20%) rated at 6 V should be
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The STK22C48 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-10 determines the 2,048 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA (Read cycle 1). If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (Read cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
In system power mode, both VCC and VCAP are connected to the +5 V power supply without the 68 F capacitor. In this mode, the AutoStore function of the STK22C48 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6 V during the 10 ms STORE cycle.
To prevent unneeded STORE operations, automatic STOREs and those initiated by externally driving HSB LOW are ignored, unless at least one WRITE operation takes place since the most recent STORE or RECALL cycle. An optional pull-up resistor is shown connected to HSB. This is used to signal the system that the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then VCC is tied to ground and +5 V is applied to VCAP (Figure 3 on page 5). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK22C48 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered with the HSB pin. It is not permissible to change between these three options "on the fly".
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Figure 3. AutoStore Inhibit Mode
Data Protection
The STK22C48 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the STK22C48 is in a Write mode (both CE and WE are low) at power-up after a RECALL or after a STORE, the Write is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power-up or brown out conditions.
Noise Considerations
The STK22C48 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
The STK22C48 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK22C48 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a Write to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. Pull-up this pin with an external 10 K ohm resistor to VCAP if HSB is used as a driver. SRAM Read and Write operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK22C48 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM Read operations take place. If a Write is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated, the STK22C48 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK22C48 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power-up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
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Hardware STORE (HSB) Operation
The STK22C48 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage conditions. When VCAPLow Average Active Power
CMOS technology provides the STK22C48 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 on page 6 shows the relationship between ICC and Read or Write cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5 V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK22C48 depends on the following items:

The duty cycle of chip enable The overall cycle rate for accesses The ratio of Reads to Writes CMOS versus TTL input levels The operating temperature The VCC level I/O loading
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Figure 4. Current Versus Cycle Time (Read) device drives HSB LOW for 20 ns at the onset of a STORE. When the STK22C48 is connected for AutoStore operation (system VCC connected to VCC and a 68 F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK22C48 attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and abort the STORE attempt.
Best Practices
nvSRAM products have been used effectively for over 15 years. While ease of use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
Preventing Store
The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2 V, because it must overpower the internal pull-down device. This Table 2. Hardware Mode Selection CE H L L X WE X H L X
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Power-up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on).
The VCAP value specified in this data sheet includes a minimum and a maximum value size. The best practice is to meet this requirement and not exceed the maximum VCAP value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers who want to use a larger VCAP value to make sure there is extra store charge should discuss their VCAP size selection with Cypress.
HSB H H H L
A10-A0 X X X X
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Figure 5. Current Versus Cycle Time (Write)
The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product's firmware should not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
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I/O Output high Z Output data Input data Output high Z
Power Standby Active[1] Active ICC2[2]
Notes 1. I/O state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE. 2. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode, inhibiting all operations until HSB rises.
Document Number: 001-51000 Rev. *D
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Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Temperature under bias............................ -55 C to +125 C Supply voltage on VCC relative to VSS ............-0.5 V to 7.0 V Voltage on input relative to VSS ........... -0.6 V to VCC + 0.5 V Voltage on DQ0-7 or HSB .....................-0.5 V to Vcc + 0.5 V Power dissipation ........................................................ 1.0 W DC output current (1 output at a time, 1 s duration) .... 15 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0 C to +70 C -40 C to +85 C VCC 4.5 V to 5.5 V 4.5 V to 5.5 V
DC Electrical Characteristics
Parameter Description Average VCC current ICC1
Over the operating range (VCC = 4.5 V to 5.5 V) [3] Test Conditions tRC = 25 ns Commercial tRC = 45 ns Dependent on output loading and cycle rate. Industrial Values obtained without output loads. IOUT = 0 mA. Average VCC current during All inputs Do Not Care, VCC = Max STORE Average current for duration tSTORE Average VCC current at WE > (VCC - 0.2 V). All other inputs cycling. tRC = 200 ns, 5 V, 25 C typical Dependent on output loading and cycle rate. Values obtained without output loads. Average VCAP current during All inputs Do Not Care, VCC = Max AutoStore cycle Average current for duration tSTORE Average Vcc current tRC = 25 ns, CE > VIH Commercial tRC = 45 ns, CE > VIH (Standby, cycling TTL input levels) Industrial Min - - - - Max 85 65 90 65 3 10 Unit mA mA mA mA mA mA
ICC2 ICC3 ICC4 ISB1[4]
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- - - -
2 25 18 26 19 1.5
mA mA mA mA mA mA A A
ISB2[4] IILK IOLK VIH VIL VOH VOL VBL VCAP
VCC standby current
Input leakage current Off state output leakage current Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Logic `0' voltage on HSB output Storage capacitor
CE > (VCC - 0.2 V). All others VIN < 0.2 V or > (VCC - 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
-1 -5
+1 +5
IOUT = -4 mA except HSB IOUT = 8 mA except HSB IOUT = 3 mA Between VCAP pin and Vss, 6 V rated. 68 F -10%, +20% nom.
2.2 VCC + 0.5 V VSS - 0.5 0.8 V 2.4 - V - 0.4 V - 0.4 V 61 220 F
Data Retention and Endurance
Parameter DATAR NVC Data retention Nonvolatile STORE operations Description Min 100 1,000 Unit Years K
Notes 3. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 4. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
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Capacitance
Parameter CIN COUT
In the following table, the capacitance parameters are listed.[5] Description Input capacitance Output capacitance TA = 25 C, f = 1 MHz, VCC = 0 to 3.0 V Test Conditions Max 8 7 Unit pF pF
Thermal Resistance
Parameter
In the following table, the thermal resistance parameters are listed.[5] Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 28-SOIC (300 mil) TBD TBD 28-SOIC (330 mil) TBD TBD Unit C/W C/W
JA JC
5.0 V Output 30 pF R2 512 Output
5.0 V
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Figure 6. AC Test Loads
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AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V Input rise and fall times (10% to 90%)......................... < 5 ns Input and output timing reference levels ....................... 1.5 V
Note 5. These parameters are guaranteed by design and are not tested.
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AC Switching Characteristics
SRAM Read Cycle
Parameter Cypress Alt Parameter tELQV tACE [6] tAVAV, tELEH tRC tAVQV tAA [7] tGLQV tDOE [7] tAXQX tOHA tELQX tLZCE [8] tEHQZ tHZCE [8] tGLQX tLZOE [8] [8] tGHQZ tHZOE tPU [9] tELICCH tEHICCL tPD [9] 25 ns Description Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Output disable to output inactive Chip enable to power active Chip disable to power standby Min - 25 - - 5 5 - 0 - 0 - Max 25 - 25 10 - - 10 - 10 - 25 45 ns Min - 45 - - 5 5 - 0 - 0 - Max 45 - 45 20 - - 15 - 15 - 45 Unit ns ns ns ns ns ns ns ns ns ns ns
Figure 7. SRAM Read Cycle 1: Address Controlled [6, 7]
Notes 6. WE and HSB must be High during SRAM Read cycles. 7. Device is continuously selected with CE and OE both Low. 8. Measured 200 mV from steady state output voltage. 9. These parameters are guaranteed by design and are not tested.
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Figure 8. SRAM Read Cycle 2: CE and OE Controlled [6]
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SRAM Write Cycle
Parameter Cypress Parameter tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [10, 11] tLZWE [10] Alt tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX Description Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write 25 ns Min 25 20 20 10 0 20 0 0 - 5 Max - - - - - - - - 10 - 45 ns Min 45 30 30 15 0 30 0 0 - 5 Max - - - - - - - - 14 - Unit ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 9. SRAM Write Cycle 1: WE Controlled [12, 13]
ADDRESS
CE
WE
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tSA
tPWE
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DATA VALID
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HIGH IMPEDANCE
tWC
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DATA OUT
PREVIOUS DATA
Figure 10. SRAM Write Cycle 2: CE Controlled [12, 13]
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Notes 10. Measured 200 mV from steady state output voltage. 11. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 12. HSB must be high during SRAM Write cycles. 13. CE or WE must be greater than VIH during address transitions.
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AutoStore or Power Up RECALL
Parameter tHRECALL [14] tSTORE [15, 16] tDELAY [17] VSWITCH VRESET tVSBL[18] Alt tRESTORE tHLHZ tHLQZ , tBLQZ Description Power Up RECALL duration STORE cycle duration Time allowed to complete SRAM cycle Low voltage trigger level Low voltage reset level Low voltage trigger (VSWITCH) to HSB Low STK22C48 Min Max - 550 - 10 1 - 4.0 4.5 - 3.6 - 300 Unit s ms s V V ns
Switching Waveform
Figure 11. AutoStore/Power Up RECALL
WE
Notes 14. tHRECALL starts from the time VCC rises above VSWITCH. 15. CE and OE low and WE high for output behavior. 16. HSB is asserted low for 1us when VCAP drops through VSWITCH. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store takes place. 17. CE and OE low for output behavior. 18. HSB must be high during SRAM Write cycles.
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Hardware STORE Cycle
Parameter tDHSB [19, 20] tPHSB tHLBL Alt Description STK22C48 Min - 15 - Max 700 - 300 Unit ns ns ns
tRECOVER, tHHQX Hardware STORE HIGH to inhibit off tHLHX Hardware STORE pulse width Hardware STORE LOW to STORE busy
Switching Waveform
Figure 12. Hardware STORE Cycle
Notes 19. CE and OE low and WE high for output behavior. 20. tDHSB is only applicable after tSTORE is complete.
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Ordering Code Definitions
STK22C48 - N F 45 I TR
Packaging Option: TR = Tape and Reel Blank = Tube
Temperature Range: Blank - Commercial (0 C to 70 C) I - Industrial (-40 C to 85 C)
Speed: 25 - 25 ns 45 - 45 ns
Lead Finish F = 100% Sn (Matte Tin) Package: N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 330 mil SOIC
Ordering Information
Speed (ns) 25
These parts are not recommended for new designs. They are in production to support ongoing production programs only. Ordering Code STK22C48-NF25ITR STK22C48-NF25I STK22C48-SF25I 45 STK22C48-NF45 STK22C48-SF25ITR STK22C48-NF45TR Package Diagram 51-85026 51-85026 Package Type Operating Range Industrial 28-pin SOIC (300 mil) 28-pin SOIC (300 mil)
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51-85058 51-85026
28-pin SOIC (330 mil) 28-pin SOIC (330 mil) Commercial
51-85058 51-85026
28-pin SOIC (300 mil) 28-pin SOIC (300 mil)
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
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Package Diagrams
Figure 13. 28-Pin (300 mil) SOIC (51-85026)
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51-85026-*E
51-85026 *F
Figure 14. 28-Pin (330 mil) SOIC (51-85058)
51-85058 *B
51-85058-*A
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Document Conventions
Acronyms
Acronym CMOS EIA I/O nvSRAM RoHS SOIC Description Complementary metal oxide semiconductor Electronic Industries Alliance Input/output nonvolatile static random access memory Restriction of hazardous substances Small outline integrated circuit
Units of Measure
C Hz kbit K A mA F MHz s ms ns pF V W degree Celsius Hertz 1024 bits kilo ohms micro Amperes milli Amperes micro Farads mega Hertz
micro seconds milli seconds pico Farads Volts ohms nano seconds
Watts
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Unit of Measure
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STK22C48
Document History Page
Document Title: STK22C48 16-Kbit (2 K x 8) AutoStoreTM nvSRAM Document Number: 001-51000 Rev. ** *A ECN No. 2625139 2826441 Orig. of Change GVCH/PYRS GVCH Submission Date 01/30/2009 12/11/2009 New data sheet Added following text in the Ordering Information section: "These parts are not recommended for new designs. In production to support ongoing production programs only." Added watermark in PDF stating "Not recommended for new designs. In production to support ongoing production programs only." Added Contents on page 2. Added Pin Configurations and Pin Definitions table. Updated Package Diagrams. Added Acronyms and units Units of Measure table. Minor edits. Removed inactive parts - STK22C48-NF25, STK22C48-NF25TR, STK22C48-SF25, STK22C48-SF25TR, STK22C48-SF45, STK22C48-SF45TR, STK22C48-NF45I, STK22C48-NF45ITR from Ordering information table. Updated Package diagrams. Added watermark in PDF stating "Not recommended for new designs. In production to support ongoing production programs only." Description of Change
*B
3037216
GVCH
09/23/2010
Document Number: 001-51000 Rev. *D
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3189527
GVCH
03/07/2011
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3054310
GVCH/KEER
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(c) Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51000 Rev. *D
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Revised March 7, 2011
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